Recently there has been a move toward so-called heterogeneous computing in which multiple processors are interconnected into one system. In some instances, tasks may be shared amongst the processors. Some of the jobs may be better suited to particular a type of processor, such as a central processing unit (CPU), graphics processing unit (GPU), or digital signal processor (DSP). Each processor involved in performing heterogeneous tasks may have one or more caches. Each cache may contain a copy of variable data that is shared among multiple processors. The caches may allow the processors to speed program execution by making the cached data more quickly accessible to one or more execution units of the processor. When one processor accesses shared variable data that is shared among two or more caches of the processors of the system, a mechanism, referred to as a “cache coherency system,” ensures that the copies of the shared variable data stored in the processor caches are consistent among all of the processors of the system, and that changes to the shared variable data are made observable to all processors sharing these variables in a timely and consistent fashion.